Many battery-powered portable electronic devices, such as laptop computers, Portable Digital Assistants, cell phones, and the like, require memory devices that provide large storage capacity and low power consumption. To reduce the power consumption and thereby extend the operating time of such devices between recharges, the devices typically operate in a low-power mode when the device is not being used. In the low-power mode, a supply voltage or voltages applied to electronic components such as a microprocessor, associated control chips, and memory devices are typically reduced to lower the power consumption of the components, as will be appreciated by those skilled in the art. Although the supply voltages are varied to reduce power consumption in the low-power mode, data stored in the electronic components such as the memory devices must be retained.
A large storage capacity is typically desired in these devices to maximize the amount of available storage. For this reasons, it is usually desirable to utilize dynamic random access memory (“DRAM”) devices, which have a relatively large storage capacity, over other types of memories such as static random access memory (“SRAM”) devices and non-volatile memories such as FLASH memory devices. However, DRAM devices have the disadvantage that their memory cells must be continually refreshed because of the means by which they store data. Refreshing DRAM memory cells tends to consume power at a substantial rate. As is well-known in the art, DRAM memory cells each consists of a capacitor that is charged to one of two voltages to store a bit of data. Charge leaks from the capacitor by various means. It is for this reason that DRAM memory cells must be refreshed by recharging them to the original voltage. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. This refresh is generally performed on a row-by-row basis at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Each time a row of memory cells is refreshed, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated, which consumes a significant amount power. As the number of columns in the memory cell array increases with increasing memory capacity, the power consumed in actuating each row increases accordingly.
The amount of power consumed by refresh also depends on which of several refresh modes is active. A Self Refresh mode is normally active during periods when data are not being read from or written to the DRAM device. Since portable electronic devices are often inactive for substantial periods of time, the amount of power consumed during Self Refresh can be an important factor in determining how long the electronic device can be used between battery charges.
The amount of power consumed by refreshing DRAM devices in any refresh mode is proportional to the rate at which it is necessary to perform refreshes. If the required refresh rate for a DRAM device could be reduced, so also could the refresh power consumption. The required refresh rate is determined by the rate at which charge leaks from the memory cell capacitors. Therefore, some attempts to increase the time required between refreshes have focused on adjusting the rate of refresh as a function of the rate of charge leakage from memory cell capacitors. For example, since the rate at which charge leaks from memory cells capacitors is a function of temperature, some power saving techniques adjust the refresh rate as a function of temperature. As a result, refreshes do not occur more frequently than necessary.
Other attempts to increase the time required between refreshes have focused on reducing the amount of charge leakage from memory cell capacitors. With reference to FIG. 1, a portion of a typical DRAM array 100 includes a plurality of memory cells 110, each of which is coupled to a word line WL and a digit line DL. The memory cells 110 in the array 100 are arranged in rows and columns, with a word line being provided for each row of memory cells 100. The word lines WL are coupled to and actuated by a row decoder 112 responsive to a row address A0-AX. As shown in FIG. 1, the DRAM array 100 has a folded digit line architecture so that complimentary digit lines DL and DL* are provided for each column of memory cells 110. In a memory array having an open digit line architecture (not shown), a single digit line DL is included in the array for each column of memory cells 110. The other digit line is provided by an adjacent array. However, the following discussion of the problems with DRAM arrays and prior attempts to solve such problems is applicable to arrays having an open digit line architecture as well as arrays having a folded digit line architecture.
Regardless of whether the array has a folded digit line architecture or an open digit line architecture, each memory cell 110 includes a memory cell capacitor 114 coupled between a cell plate 116 and a storage node 118. The cell plate is normally common to all of the memory cells 110 in an array, and it is generally biased to a voltage of VCC/2. An access transistor 120 is coupled between the storage node 118 and a digit line DL for the column containing the memory cell 110. The gate of the access transistor 120 is coupled to a word line WL for the row containing the memory cell 110. When a data bit is to be written to the memory cell 110, a voltage corresponding to the data bit, generally either VCC or zero volts, is applied to the digit line DL to which the memory cell 110 is coupled, and the voltage applied to the word line WL is driven high to turn ON the access transistor 120. The access transistor then couples the digit line DL to the capacitor 114 to store the voltage of the digit line DL in the capacitor 114. For a read operation, the digit line DL is first equilibrated to an equilibration voltage, generally to VCC/2, and the word line WL is then driven high to turn ON the access transistor 120. The access transistor 120 then couples the capacitor 114 to the digit line DL to slightly alter the voltage on the digit line DL above or below the equilibration voltage depending upon the voltage stored in the capacitor 114. An n-sense amplifier 130 and a p-sense amplifier 132 sense whether the voltage has increased or decreased responsive to applying an active low NSENSE* signal of normally zero volts to the n-sense amplifier 130 and applying an active high PSENSE signal of normally VCC to the p-sense amplifier 132. The NSENSE* signal and the PSENSE signal are supplied by control circuitry (not shown) in a DRAM. If a voltage increase was sensed, the p-sense amplifier 132 drives the digit line DL to VCC, and, if a voltage decrease was sensed, the n-sense amplifier 130 drives the digit line DL to zero volts. The voltage applied to the digit line DL by the sense amplifiers 130, 132 then recharges the capacitor 114 to the voltage to which it was originally charged. A column decoder 136 couples one of the pairs of complimentary digit lines DL, DL* to complimentary input/output lines “IO, IO*” responsive to a column address A0-AY.
The above-described memory read process of activating a word line WL and then sensing the digit line voltage of all memory cells 100 in the row for the active word line WL is what is done to refresh the memory cells 100. If the voltage on the capacitor 114 has been excessively discharged from VCC or excessively charged from zero volts between refreshes, it can be impossible for the sense amplifiers 130, 132 to accurately read the voltage to which the memory cell capacitor 114 was charged. The result is an erroneous reading of the memory cell 100 known as a data retention error.
As is well known in the art, the charge placed on a memory cell capacitor 114 dissipates through a variety of paths. One discharge path is through the dielectric of the capacitor 114 itself. Another significant discharge path is through the access transistors 120 coupling the capacitors 114 to the digit lines DL when the transistors 120 are turned OFF. This leakage current is known as the “sub-threshold” leakage current of the transistors 120. Reducing the sub-threshold leakage current of the access transistors 120 allows the capacitor 114s to retain a voltage that is close enough to the voltage initially placed on the capacitors 114 for a data retention error to be avoided. Various approaches have been used to reduce the sub-threshold leakage of the access transistors 120 to allow memory cell capacitors 114 to retain charge for a longer period between refreshes. Some of these approaches rely on increasing the threshold voltage VT of the access transistor 120 by either biasing the word lines to a negative voltage when the word line is not active or by biasing the substrate to a less negative voltage.
Another path through with the charge placed on a memory cell capacitor 114 can dissipates is from the access transistor 120 to the substrate. With reference to FIG. 2, a typical memory cell access transistor 120 is in NMOS transistor for up in a P-type substrate 140 having a first n-doped source/drain region 142 and a second n-doped source/drain region 144. The first n-doped source/drain region 142 is coupled to a digit line DL, and the second n-doped source/drain region 144 is coupled to a memory cell capacitor 114. The access transistor 120 also includes a gate formed by a gate electrode 146 insulated from the substrate 140 by an oxide layer 148. The gate electrode 146 is coupled to a word line WL. The n-doped source/drain region 144 that is coupled to the memory cell capacitor and the p-doped substrate 140 together form a diode junction 150, which is schematically illustrated in FIG. 3 along with the access transistor 120 and the memory cell capacitor 114. The substrate 140 is biased to a voltage VDD that is typically negative, such as −0.5 V. As previously mentioned, the cell plate 116 is typically biased to VCC/2, such as 1 V, as shown in FIG. 3. Therefore, when the memory cell capacitor 114 is charged to a voltage of VCC, which in this example is 2 V, the diode junction 150 is back-biased with a voltage of 2.5 V. Unfortunately, even though the diode junction 150 is back-biased, a significant amount of charge leaks through the diode junction 150. This charge leakage limits the period of time that the memory cell capacitor 114 can retain its charge without being refreshed. As a result, the memory cell capacitor 114 must be frequently refreshed, thereby causing a DRAM device containing the memory cell capacitor 114 to consume substantial power.
There is therefore a need for a technique to reduce the charge leakage through the diode junction 150 so that the time between required refreshes can be increased, thereby allowing DRAM devices to consume less power.